FATTED: A fatter TED

After FATVIC, the obvious next question was: what would the same idea look like on the other side of the Commodore family? The Plus/4, C16 and C116 all hang off one chip, the TED (MOS 7360/8360). It does video, sound, timers, keyboard scanning and DRAM control. That makes it the perfect place to add things, and also the one chip you really cannot get wrong.

So here is FATTED. An FPGA drop-in replacement for the TED, that behaves exactly like a stock TED until you ask it not to.

This post describes the first release of the specification (rev A.1). No hardware exists yet. This is the architecture I am going to build.

Design rules

I set a few rules before anything else:

1. Drop-in. It goes in the TED socket. No cables hanging out of the case. Size as TED DIP package. No more no less.
2. Everything you already own keeps working. Cartridges, 1551 drives and other TCBM devices, datasette, user port gadgets.
3. Stock behaviour is cycle exact. Until the extensions are unlocked, software sees an ordinary TED. Bad line CPU stalls, single/double clock switching, DRAM refresh timing on the bus. All of it.
4. Extensions are timing neutral. New video features never steal CPU cycles beyond what a stock TED already does.
5. Any modification is optional and reversible. There is exactly one optional bodge wire, and most people will never need it.

Hardware

As with FATVIC, it uses a ECP5 from Lattice FPGA. The external memory is a 8MByte HyperRAM.

NOR FLASH for configuration and EEPROM for settings, with enough room for application data.

FATTED takes over the RAM

This is the part I like most. TED already generates the DRAM control signals, so FATTED simply keeps CAS inactive. The motherboard DRAM never answers, and FATTED serves every RAM access from its own external RAM instead.

That means:

• No board modification. The original DRAM can stay in or come out.
• A C16 suddenly has 64 KB, plus the banked expansion. There is a 16 KB mirror mode for the software that depends on how a stock C16 mirrors its RAM.
• One CPU cycle at 1.77 MHz is about 565 ns, which is plenty of time for HyperRAM even in the worst case. The CPU always has a guaranteed slot.

Optional Features

Hidden until you ask

All the new video registers are hidden behind an unlock. Write "FAT" to $FF20 and a read returns $FA. Until then, reads to the new addresses are not driven, so a stock program cannot trip over them. SID and the Hannes register are the exceptions, since those have to work with existing software.

A tile layer

• One 8 bpp tile layer in A.1, with a second one reserved.
• 8×8 pixel tiles, 1024 tiles per set.
• Map size from 32×32 up to 256×256 tiles, wrapping in both directions.
• Hardware scrolling in X and Y, with changes taking effect per raster line for split scrolling.
• Per tile flip and a priority bit against sprites.
• The layer can sit in front of or behind the normal TED picture. Put it behind, and ordinary TED text becomes a free HUD over your scrolling playfield.

32 hardware sprites

• 32 sprites, all of them visible on every raster line. No per line limit, no multiplexing needed.
• 8 bits per pixel, sizes 8, 16, 32 or 64 pixels in each direction, plus pixel/line doubling.
• Horizontal and vertical flip.
• Four priority levels relative to the tile layer and the normal TED picture.
• Alpha blending through the extended palette.
• Collision detection with four collision groups. Sprites in the same group never collide with each other, so your enemies do not keep reporting hits on each other.
• Collision flags are latched once per frame. Nothing to clear.

The sprite attributes are reached through four small 8-byte windows at $FDE0–$FDFF. You pick a sprite number in the window and then read or write X, Y, pattern, flip and so on directly. With auto-increment set, one window can stream all 32 sprites with 7 writes each. Coordinates are buffered and committed on the high byte, and all changes take effect from the next raster line. So no tearing, and raster split tricks work as you would expect.

Colours

Tiles and sprites use one byte per pixel in the TED colour space: hue in the low nibble, luminance above it. TED's blink bit makes no sense for sprites and tiles, so bit 7 got a new job. With bit 7 set, the pixel instead points into a 128-entry extended palette with 12-bit RGB and 4-bit alpha. Alpha gives opaque, blended or additive pixels, and blending is done in a linear colour domain rather than on raw TED values. Palette entries can be rewritten at any time, so colour cycling is free.

4 MB of RAM, Hannes compatible

• 4 MB as 64 banks of 64 KB, with a selectable common area at the bottom (4 KB, 16 KB or just zero page and stack).
• Hannes256 compatible through the usual $FD16 register, since Hannes is by far the most common expansion scheme on the Plus/4. The upper bank bits are ignored on purpose, so games like Dream World and Lykia that trip on larger Hannes expansions just work.
• A new, clean bank register for modern software with access to all 64 banks.
• Double buffering across banks from day one. A separate video bank register lets TED show one bank while the CPU draws in another, and the swap can be deferred to the next vertical blank for a tear-free flip.

$FD16 sits in the mirror of the user port chip, so writes there also wiggle the user port pins. FATTED handles this three ways: ignore it if you use neither user port nor datasette, fit the optional bodge wire if you do and want old 256K software, or just use the new register.

Two SIDs built in

• SID1 at $FD40 (SIDcard compatible) and SID2 at $FE80 (compatible with the Hungarian SID cartridge).
• 6581 or 8580 per SID. SID2 can run independently for stereo or mirror SID1.
• Enabled by configuration, no unlock needed, so existing SID music and games work as they are.

VRAM access ports

Two indirect data ports with 24-bit addresses and a configurable auto-increment or decrement step. They see one flat address space: main RAM banks, VRAM and FATTED's internal registers. So you can copy between any memory bank and VRAM without banking the CPU at all.

Settings and the TEDDY connection

Machine specific choices (Hannes compatibility on/off, bodge fitted, C16 mirror mode, SID setup) are stored in FATTED's own flash and loaded at power-on. You set them once for your machine.

The configuration tool is the same manager that runs TEDDY, my Plus/4 cartridge. One application configures both. If TEDDY is not fitted, the same code will also be built as a stand-alone PRG. On the TEDDY versions with a display, the current FATTED modes will be shown on the cartridge.

What is next

The next spec release adds support for the Csory banking mode and gathers all the small compatibility switches into one register, with a lock so a runaway program cannot change your machine setup by accident.

The open items I still need to close before schematics:

• Verify on real Plus/4 and C16 boards that nothing else drives the bus in the address ranges I have claimed.
• Pick the ECP5 size and package, and the HyperRAM part.
• Clocking: PLL from the machine clock, or a local oscillator like on FATVIC.
• Video DAC for the stock outputs and the VGA/audio adapter.
• Define the bodge wire.
• Tile layer 1, and a possible blitter/DMA engine in the reserved $FE00–$FE7F block.
• A per-net check of 3.3 V output levels against the 5 V logic thresholds.

More when there is copper.